1. Field of the Invention
The present invention relates to various types of output buffers for a memory circuit and, more particularly, to an output buffer circuit which selects among drive buffers of a number of drive abilities.
2. Discussion of the Related Art
Generally, a data output buffer is a device which receives input data from a memory cell, amplifies the signal, and outputs this signal. The increase in operating speed due to large-scale integration of semiconductor memory devices produces a large amount of noise. The main reason for this noise is that the transistor in the output terminal of the data output buffer produces a large peak current when it undergoes a transition while having a large channel size. This causes the source wires in the chip to produce a large amount of noise, and adversely affects the performance of the semiconductor memory device by causing malfunctions.
Impulse-like peak currents are produced at the output terminal of the data output buffer for other reasons as well. For example, the small channel of the transistor which makes up the output terminal is very large compared to other circuits. Also, the voltage undergoes a full-swing operation from a `high` source voltage to a `low` ground voltage and vice versa.
A conventional method that modifies the pull-up and pull-down driving power according to the operating frequency to avoid noise generation is shown in FIG. 1 and disclosed in U.S. Pat. No. 5,319,258.
As shown in FIG. 1, a first driver unit 12 and a second driver unit 14 are connected in parallel. In the first driver unit 12, a pull-up NMOS transistor MN1 and a pull-down NMOS transistor MN2 are connected between the source voltage Vcc and the ground voltage Vss. An output terminal DOUT is connected to a node where the source of transistor MN1 and the drain of transistor MN2 are commonly connected. In the second driver unit 14, similar to the above first driver unit 12, a pull-up NMOS transistor MNS1 and a pull-down NMOS transistor MNS2 are connected between the source voltage Vcc and the ground voltage Vss. The above output terminal DOUT is connected to a node where the source of transistor MNS1 and the drain of transistor MNS2 are commonly connected.
An input terminal INPUT where the data is received is connected to one terminal of each of AND gates 16 and 18. The other terminals of the AND gates are connected to a select signal SEL that outputs a high or low signal according to the operating frequency to enable or disable the above second driver unit 14. Also, a first buffer 20 consisting of two inverters connected serially is connected to the input terminal INPUT. The output terminal of the first buffer 20 is connected to the gate terminal of the pull-up NMOS transistor MN1 of the first driver unit 12.
At the same time, a second buffer 22 consisting of two serially connected inverters is connected to the input terminal INPUT through an inverter I1. The output terminal of the second buffer is connected to the gate terminal of the pull-down NMOS transistor MN2 of the first driver unit 12. Here, the first and second buffers 20, 22 are delay elements for overcoming the delay time related to each signal path.
In the circuit of FIG. 1 described above, a fast pull-up and pull-down is necessary at a high frequency, and a high signal is output by the select signal SEL when the driving voltage is at high voltage while a low signal is output by the select signal SEL when the driving voltage is at low voltage. In other words, for a low frequency, the select signal SEL is also low and the outputs of the AND gates 16,18 become low regardless of the input signal INPUT, and the second drive unit 14 is disabled. Therefore, only the first drive unit 12 is operated according to the input signal INPUT.
When the input signal INPUT is high, the output of the first buffer 20 is high, and since an inverted signal is input to the second buffer 22 by the inverter I1, the output of the second buffer 22 becomes low. Therefore, the pull-up transistor MN1 of the first drive unit 12 is turned on and the pull-down NMOS transistor MN2 is turned off, and the output signal DOUT becomes the source voltage Vcc. On the other hand, if the input signal INPUT is low, the pull-up NMOS transistor MN1 of the first drive unit 12 is turned off and the pull-down NMOS transistor MN2 is turned on, and the output signal DOUT becomes the ground voltage Vss. Consequently, at a low frequency, only the pull-up and pull-down NMOS transistors MN1, MN2 of the first drive unit 12 are operational, so that while the speed is slowed, the noise produced is decreased.
On the other hand, at a high frequency, the select signal SEL becomes high, and the outputs of the AND gates 16,18 become high or low according to the input signal INPUT, and the outputs of the first and second buffers 20,22 also become high or low according to the input signal INPUT. Therefore, the first drive unit 12 and the second drive unit 14 are both operated according to the input signal INPUT. In other words, when the input signal INPUT is high, the pull-up NMOS transistor MN1 of the first drive unit 12 is turned on by the first buffer 20, and simultaneously, the pull-up NMOS transistor MNS1 of the second drive unit 14 is turned on by the AND gate 16.
When the input signal is low, the pull-down NMOS transistor MN2 is turned on by the second buffer 22, and simultaneously, the pull-down NMOS transistor MNS2 of the second drive unit 14 is turned on through the AND gate 18. Here, because the first drive unit 12 and the second drive unit 14 are connected in parallel, following the operating frequency, that is, for a high frequency, fast pull-up and pull-down is carried out.
FIG. 2 is a circuit describing another example of a conventional output buffer circuit. In FIG. 2, a pull-up transistor MP1 and a pull-down transistor MN1 are connected between a source voltage Vcc and a ground voltage Vss. An output terminal DOUT is connected to the node common to the source of transistor MP1 and transistor MN1.
Further, a NOR gate NOR1 operated by an input signal RD and the inverted output of an output enable signal OE, and an inverter X2 are connected serially to the gate of the pull-up transistor MP1. A NAND gate NAND1 operated by the input signal RD and the output enable signal OE, and an inverter X3 are connected serially to the gate of the pull-down transistor MN1. Here, the output enable signal OE is input to the NOR gate NOR1 through an inverter X1 and input directly to the NAND gate NAND1.
In the circuit of FIG. 2 described above, if the output enable signal OE is low, then the output of the NOR gate NOR1 is low and the output of the NAND gate NAND1 is high, regardless of the input signal RD. Then, the low output of the NOR gate NOR1 is inverted to a high signal by the inverter X2 to turn off the pull-up transistor MP1, and the high output of the NAND gate NAND1 is inverted to a low signal by the inverter X3 to turn off the pull-down transistor MN1, so that the output DOUT becomes a high impedance state.
If, on the other hand, the output enable signal OE is high and the input signal RD is high, the outputs of the NOR gate NOR1 and the NAND gate NAND1 are both low and are inverted by the inverters X2 and X3, respectively. Accordingly, the pull-up transistor MP1 is turned off and the pull-down transistor MN1 is turned on, and the output DOUT becomes low (Vss).
If the output enable signal OE is high and the input signal RD is low, the outputs of the NOR gate NOR1 and the NAND gate NAND1 are both high and are inverted by the inverters X2 and X3, respectively. Accordingly, the pull-up transistor MP1 is turned on the pull-down transistor MN1 is turned off and the output DOUT becomes high (Vcc).
However, in FIG. 1 and FIG. 2, there are disadvantages in that at a high operating frequency, the pull-up and pull-down operations become fast, and large peak currents and a large amount of noise are generated. While at a low operating frequency, the pull-up and pull-down operations become slow.
Moreover, if the size of the driving transistors is increased to satisfy a speed condition for a low voltage, a large amount of current and much noise is generated at a high voltage.